The present invention relates generally to interconnect technology in integrated circuit fabrication, and more particularly, to a structure and method for testing for electromigration failure rate of interconnect using slotted feeder lines to prevent formation of stress-induced voids within the feeder lines.
FIG. 1 shows an interconnect test structure 100 including a test line 102, a first feeder line 104, and a second feeder line 106, according to the prior art. The test line 102, the first feeder line 104, and the second feeder line 106 are comprised of copper for example. In that case, the test line 102, the first feeder line 104, and the second feeder line 106 are each surrounded by a respective diffusion barrier layer material 112, 114, and 116.
The first feeder line 104 is coupled to a first test pad 108, and the second feeder line 106 is coupled to a second test pad 110. The test line 102 is coupled to the first feeder line 104 by a first via structure 122 at a first end of the test line 102, and the test line 102 is coupled to the second feeder line 106 by a second via structure 124 at a second end of the test line 102. The first and second via structures 122 and 124 may each be comprised of copper according to the prior art.
FIG. 2 shows a top view of the interconnect test structure 100 of FIG. 1 that is used for characterizing electromigration failure rate of the test line 102. The first and second feeder lines 104 and 106 each have a width, wf, 162 that is substantially greater than a width, wt, 164 of the test line 102. For example, the width, wf, 162, of the first and second feeder lines 104 and 106 is at least about ten times greater than the width, wt, 164 of the test line 102. A current source 206 and a resistance meter 208 are coupled between the first and second test pads 108 and 110. A processor 212 and a timer 210 monitor the resistance across the first and second test pads 108 and 110 as current is conducted through the first feeder line 104, the test line 102, and the second feeder line 106.
The first feeder line 104 is a source of electrons (i.e., a cathode) flowing into the test line 102, and the second feeder line 106 is a sink of electrons (i.e., an anode) flowing out of the test line 102. For characterizing the electromigration failure rate of the test line 102, a current is conducted through the test line 102 with a current density, J. A length, L, 103 of the test line 102 and the current density, J, through the test line 102 are designed such that the product of such values (J*L) is greater than a critical Blech length constant (J*L)CRIT corresponding to the test line 102. The critical Blech length constant (J*L)CRIT is a constant for an interconnect line depending on various processing parameters for the interconnect line such as the material comprising the interconnect line and the material surrounding the interconnect line for example, as known to one of ordinary skill in the art of integrated circuit fabrication.
When the current density, J, and the length, L, for an interconnect line arc designed such that the product of such values (J*L) is less than the critical Blech length constant (J*L)CRIT, then that interconnect line is immortal and does not exhibit electromigration failure, as known to one of ordinary skill in the art of integrated circuit fabrication. On the other hand, when the current density, J, and the length, L, for an interconnect line are designed such that the product of such values (J*L) is greater than the critical Blech length constant (J*L)CRIT, the interconnect line does exhibit electromigration failure.
For characterizing the electromigration failure rate of the test line 102, with the current density, J, and the length, L, for the test line 102 being designed such that the product of such values (J*L) is greater than the critical Blech length constant (J*L)CRIT for the test line 102, an electromigration life-time is determined when the resistance measured by the resistance meter 208 reaches a threshold resistance level, as known to one of ordinary skill in the art of integrated circuit fabrication. Referring to FIG. 1, the test line 102 exhibits such electromigration failure from formation of an electromigration void 123 within the test line 102 that typically causes the resistance of the test line 102 to rise sharply.
To ensure that the electromigration void 123 is formed within the test line 102 and not within the feeder lines 104 and 106 when characterizing the test line 102, the width, wf, 162, of each of the first and second feeder lines 104 and 106 is designed to be substantially greater (such as at least about ten times greater) than the width, wt, 164 of the test line 102. However, as described in the journal article, Stress-Induced Voiding under Vias Connected to Wide Cu Metal Leads, Proc. of IEEE International Reliability Physics Symposium, pp. 312-321 (2002), to E. T. Ogawa et al., with such large widths, wf, 162, of the feeder lines 104 and 106, although such feeder lines 104 and 106 do not exhibit electromigration failure, stress-induced voids 125 tend to form at the interface between such feeder lines 104 and 106 and a respective one of the first and second via structures 122 and 124.
With formation of such stress-induced voids 125 within the feeder lines 104 and 106, the increase in resistance as measured by the resistance meter 208 can no longer be attributable solely to electromigration failure within the test line 102. Thus, because of formation of such stress-induced voids 125 within the feeder lines 104 and 106, electromigration failure rate of the test line 102 cannot be characterized with the interconnect test structure 100 of the prior art.
Nevertheless, accurate characterization of electromigration failure rate of the test line 102 is desired. Thus, a interconnect test structure is needed for accurately characterizing electromigration failure rate of the test line 102 of the interconnect test structure without formation of stress-induced voids within the feeder lines 104 and 106.
Accordingly, in a general aspect of the present invention, feeder lines of an interconnect test structure are formed to be slotted to prevent formation of stress-induced voids therein during characterization of electromigration failure rate of the test line of the interconnect test structure.
In one embodiment of the present invention, an interconnect test structure used for characterizing electromigration failure rate of interconnect includes a test line comprised of a conductive material and having a current density, J. and a length, L. A product of the current density and the length of the test line, J*L, is greater than a critical Blech length constant, (J*L)CRIT, for the test line. The interconnect test structure further includes a first feeder line comprised of a conductive material and coupled to the test line at a first end of the test line. The first feeder line is a source of electrons flowing into the test line. The interconnect test structure also includes a second feeder line comprised of a conductive material and coupled to the test line at a second end of the test line. The second feeder line is a sink of electrons flowing from the test line. A width of each of the first and second feeder lines is greater than a width of the test line.
In addition, the interconnect test structure includes a first via structure disposed between the first feeder line and the test line, and includes a second via structure disposed between the second feeder line and the test line. At least one of the first and second feeder lines has at least one slot formed therein for preventing formation of a stress-induced void at an interface between the feeder line having the slot formed therein and a respective one of the first and second via structures.
In this manner, formation of at least one slot within a feeder line reduces the volume of the feeder line. With such reduced volume of the feeder line, formation of a stress-induced void at the interface of the feeder line and a via structure on the feeder line is prevented. In addition, the width of the feeder line is still maintained to be substantially larger than the width of the test line to prevent electromigration failure of the feeder line. Thus, an increase in resistance across the feeder lines and the test line may be attributed to electromigration failure of the test line from formation of an electromigration void within the test line such that the electromigration failure rate of the test line may be accurately characterized.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.